1. Field of the Invention
The present invention relates to a solid-state imaging device, and, more particularly, to a solid-state imaging device having a memory to be used at the time of performing a correction process.
2. Description of the Related Art
A solid-state imaging device for use in a cellular phone, a digital still camera, etc. has a memory which is used at the time of performing a correction process. There is a solid-state imaging device in which a memory test circuit for testing such a memory is connected to the memory (see, for example, JP-A-2004-93421 (Patent Document 1)).
FIG. 7 shows the configuration of an electronic circuit having a memory test circuit according to a related art. As shown in FIG. 7, an electronic circuit 50 includes a signal processing section 51, a control circuit 52, a control interface (I/F) 53, a memory 54, a data interface (I/F) 55, and memory test circuit 56. The memory test circuit 56 includes a BIST circuit 57, and a JTAG interface (I/F) 58.
The control circuit 52 performs the general control of the electronic circuit 50 based on a control signal input via the control interface 53. The signal processing section 51 performs writing/reading of predetermined data in/from the memory 54, and performs predetermined signal processing on the data which is in turn output via the data interface 55.
The BIST circuit 57 generates a test pattern for testing the memory 54 based on a control signal input via the JTAG interface 58, and tests the memory 54 based on the test pattern. The result of the test is output to a tester 60 via the JTAG interface 58.